For sale is one i960MX CPU die. These were from a wafer that was factory diced, but never made it to final packaging.This MX version of the i960 was only sold to military customers. If you look at the commercial i960 versions they are all functionally subsets of the MX. Believe it or not, the i960MX was already obsolete and out of production when it was put into the F-22 raptor. This is often the case in the military hardware, as the design and qualification cycles are so long. The central i960 instruction-set architecture was a RISC design, which was only implemented in full in the i960MX. The memory subsystem was 33-bits wide—to accommodate a 32-bit word and a "tag" bit to implement memory protection in hardware. In many ways, the i960 followed the original Berkley RISC design, notably in its use of register windows, an implementation-specific number of caches for the per-subroutine registers that allowed for fast subroutine calls. The competing Stanford University MIPS design did not use this system, instead relying on the compiler to generate optimal subroutine call and return code. In common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no memory segmentation, except for the i960MX, which could support up to 226 "objects", each up to 232 bytes in size. The i960 architecture also anticipated a superscalar implementation, with instructions being simultaneously dispatched to more than one unit within the processor.
The dies are large and beautiful, much better than the photo shows. They are 15mm x 17mm and in perfect condition for collection, display, or mounting in jewelry.
See many other tech collectibles in my store.

Will ship well packaged to protect from damage.

Detailed die photo credit: Pauli for looking!